Job Description

Marvell Physical Design Engineer

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Marvell's custom ASIC offering specializes in addressing the complex, high-speed, high-performance silicon requirements of next generation data center applications. The Marvell Physical Design team located in our Rochester, MN office has a long history of successful design tapeouts in advanced process nodes. Our team is made up of engineers with a broad depth of static timing analysis and physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you'll have the opportunity to work on timing analysis for future designs of our next-generation, high-performance data center chips in a leading-edge CMOS process technology.

What You Can Expect:

• Assist in performing static timing analysis on digital designs using industry-standard EDA tools (e.g., PrimeTime, Tempus).
• Help develop and validate timing constraints (SDC) for various design blocks.
• Support timing closure efforts by identifying and resolving timing violations.
• Collaborate with RTL, synthesis, and physical design teams to understand timing bottlenecks.
• Contribute to automation scripts and flows to improve STA efficiency and accuracy.
• Document findings and present results to the team.

What We're Looking For:

• Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of digital logic design and timing concepts (setup/hold, clock skew, etc.).
• Familiarity with Verilog and basic scripting languages (e.g., Python, Tcl, or Perl).
• Coursework or project experience in VLSI design or digital IC design is a plus.
• Excellent problem-solving and communication skills.

Preferred Qualifications:

• Exposure to STA tools or timing analysis in academic projects.
• Knowledge of CMOS technology and physical design flow.
• Passion for learning and working in a fast-paced, collaborative environment.

Expected Base Pay Range (USD): 28 - 55 per hour.

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements:

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental, and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days, and paid sick time. Additional compensation may be available for intern PhD candidates.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability, or protected veteran status.

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